The fabrication of various solid state devices requires the use of planar substrates, or semiconductor wafers, on which integrated circuits are fabricated. The final number, or yield, of functional integrated circuits on a wafer at the end of the IC fabrication process is of utmost importance to semiconductor manufacturers, and increasing the yield of circuits on the wafer is the main goal of semiconductor fabrication. After packaging, the circuits on the wafers are tested, wherein non-functional dies are marked using an inking process and the functional dies on the wafer are separated and sold. IC fabricators increase the yield of dies on a wafer by exploiting economies of scale. Over 1000 dies may be formed on a single wafer which measures from six to twelve inches in diameter.
Various processing steps are used to fabricate integrated circuits on a semiconductor wafer. These steps include deposition of a conducting layer on the silicon wafer substrate; formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal interconnection pattern, using standard lithographic or photolithographic techniques; subjecting the wafer substrate to a dry etching process to remove the conducting layer from the areas not covered by the mask, thereby etching the conducting layer in the form of the masked pattern on the substrate; removing or stripping the mask layer from the substrate typically using reactive plasma and chlorine gas, thereby exposing the top surface of the conductive interconnect layer; and cooling and drying the wafer substrate by applying water and nitrogen gas to the wafer substrate.
The numerous processing steps outlined above are used to cumulatively apply multiple electrically conductive and insulative layers on the wafer and pattern the layers to form the circuits. The final yield of functional circuits on the wafer depends on proper application of each layer during the process steps. Proper application of those layers depends, in turn, on coating the material in a uniform spread over the surface of the wafer in an economical and efficient manner.
In the semiconductor industry, copper is being increasingly used as the interconnect material for microchip fabrication. The conventional method of depositing a metal conducting layer and then etching the layer in the pattern of the desired metal line interconnects and vias cannot be used with copper because copper is not suitable for dry-etching. Special considerations must also be undertaken in order to prevent diffusion of copper into silicon during processing. Therefore, the dual-damascene process has been developed and is widely used to form copper metal line interconnects and vias in semiconductor technology. In the dual-damascene process, the dielectric layer rather than the metal layer is etched to form trenches and vias, after which the metal is deposited into the trenches and vias to form the desired interconnects. Finally, the deposited copper is subjected to chemical mechanical planarization (CMP) to remove excess copper (copper overburden) extending from the trenches.
A significant advantage of the dual-damascene process is the creation of a two-leveled metal inlay which includes both via holes and metal line trenches that undergo copper fill at the same time. This eliminates the requirement of forming the trenches for the metal interconnect lines and the holes for the vias in separate processing steps. The process further eliminates the interface between the vias and the metal lines.
Another important advantage of the dual-damascene process is that completion of the process typically requires 20% to 30% fewer steps than the traditional aluminum metal interconnect process. Furthermore, the dual damascene process omits some of the more difficult steps of traditional aluminum metallization, including aluminum etch and many of the tungsten and dielectric CMP steps. Reducing the number of process steps required for semiconductor fabrication significantly improves the yield of the fabrication process, since fewer process steps translate into fewer sources of error that reduce yield.
Electroplated copper provides several advantages over electroplated aluminum when used in integrated circuit (IC) applications, including dual damascene applications. Copper is less electrically resistive than aluminum and is thus capable of higher frequencies of operation. Furthermore, copper is more resistant to electromigration (EM) than is aluminum. This provides an overall enhancement in the reliability of semiconductor devices because circuits which have higher current densities and/or lower resistance to EM have a tendency to develop voids or open circuits in their metallic interconnects. These voids or open circuits may cause device failure or burn-in.
FIG. 1 schematically illustrates a typical standard or conventional electrochemical plating (ECP) system 10 for depositing copper onto a semiconductor wafer 18. The ECP system 10 includes a standard electroplating cell having an adjustable current source 12, a bath container 14, a copper anode 16 and a cathode 18, which cathode 18 is the semiconductor wafer that is to be electroplated with copper. The anode 16 and semiconductor wafer/cathode 18 are connected to the current source 12 by means of suitable wiring 38. The bath container 14 holds a bath 20 typically of acid copper sulfate solution which may include an additive for filling of submicron features and leveling the surface of the copper electroplated on the wafer 18.
As illustrated in FIGS. 1 and 2, the ECP system 10 typically further includes a pair of bypass filter conduits 24 which extend through the anode 16 and open to the upper, oxidizing surface 22 of the anode 16 at opposite ends of the anode 16. The bypass filter conduits 24 connect to a bypass pump/filter 30 located outside the bath container 14, and the bypass pump/filter 30 is further connected to an electrolyte holding tank 34 through a tank inlet line 32. The electrolyte holding tank 34 is, in turn, connected to the bath container 14 through a tank outlet line 36.
In operation of the ECP system 10, the current source 12 applies a selected voltage potential typically at room temperature between the anode 16 and the cathode/wafer 18. This potential creates a magnetic field around the anode 16 and the cathode/wafer 18, which magnetic field affects the distribution of the copper ions in the bath 20. In a typical copper electroplating application, a voltage potential of about 2 volts may be applied for about 2 minutes, and a current of about 4.5 amps flows between the anode 16 and the cathode/wafer 18. Consequently, copper is oxidized typically at the oxidizing surface 22 of the anode 16 as electrons from the copper anode 16 reduce the ionic copper in the copper sulfate solution bath 20 to form a copper electroplate (not illustrated) at the interface between the cathode/wafer 18 and the copper sulfate bath 20.
The copper oxidation reaction which takes place at the oxidizing surface 22 of the anode 16 is illustrated by the following reaction formula (1):Cu - - - >Cu+++2e−  (1)
The oxidized copper cation reaction product forms ionic copper sulfate in solution with the sulfate anion in the bath 20:Cu+++SO4−− - - - >Cu++SO4−−  (2)
At the cathode/wafer 18, the electrons harvested from the anode 16 flow through the wiring 38 and reduce copper cations in solution in the copper sulfate bath 20 to electroplate the reduced copper onto the cathode/wafer 18:Cu+++2e− - - - >Cu  (3)
Throughout the copper ECP process, the copper is deposited on all areas of the wafer surface, as well as the wafer edge. Thus, a wafer edge removal process, commonly known as IBC (Integrated Bevel Clean), is typically carried out on the wafer to remove the excess electroplated copper from the edge of the wafer. Typically, the IBC module in which the edge removal process is carried out is integrated into the ECP machine which contains the ECP bath in which the electrochemical copper plating process is carried out. However, the IBC module occupies a relatively large footprint in the semiconductor fabrication facility. Furthermore, because the IBC process is separate from the the ECP process, the electroplated wafers must be individually transported from the ECP bath to the IBC module, and this adversely affects wafer throughput. Accordingly, a device and method is needed for preventing electroplating of copper or other metal on the edge of a wafer to eliminate the need for the IBC process to be carried out on the wafer after the ECP process.
An object of the present invention is to provide a novel dual contact ring for removing metal electrochemically plated onto the outer, edge region of a substrate while facilitating plating of the metal onto the inner, central region of the substrate.
Another object of the present invention is to provide a novel dual contact ring which enhances wafer throughput in the fabrication of semiconductor integrated circuits.
Still another object of the present invention is to provide a novel dual contact ring which enhances space utilization in a semiconductor fabrication facility.
Yet another object of the present invention is to provide a novel dual contact ring which may include an outer voltage ring for contacting the edge regions of a substrate, an inner voltage ring for contacting the central regions of the substrate, and a voltage source connected to the outer voltage ring and the inner voltage ring for applying a positive voltage to the outer voltage ring and a negative voltage to the inner voltage ring.
A still further object of the present invention is to provide a method for plating a metal onto the central, patterned region of a substrate and de-plating a metal from the outer, edge region of a substrate.